| What_is_CISC? Defines term, lists other Webpages to learn more. Webopedia. |
| TRON_VLSI_CPU CISC 32-bit processor architecture developed to serve as main hardware building block of the realtime TRON Hypernetwork (Highly Functional Distributed System: HFDS), the ultimate goal of the TRON Proj |
| High_Performance_Computing__CISC_vs__RISC Brief introduction, gives general idea of what CISC and RISC are. |
| Hyperstone_Electronics_GmbH RISC/DSP processors, flash memory controllers and cards (and compact cards), ASIC design, IP hardware, biometric devices, digital still cameras. |
| John_Mashey_on_RISC/CISC From comp.arch debates, in one text document for easier reading, original text and formats preserved, mostly. |
| Reduced_Instruction_Set_Computer Brief, very clear definition, with links to related issues and processors. [FOLDOC] |
| RISC_Architecture Sophomore college project. Basic clear explanations of: What is RISC, MIPS processors, Pipelining, RISC vs. CISC, some recent developments, readings. |
| RISC__Reduced_Instruction_Set_Computer Acronym finder, has several similar, complementary definitions. |
| RISC_vs__CISC Document based on John Mashey (SGI) compilation of comp.arch debates, in one HTML document for easier reading, more so tables; original text and formats preserved where possible. |
| What_is_RISC? Defines term, lists other Webpages to learn more. Webopedia. |
| Wikipedia__Reduced_Instruction_Set_Computer Online encyclopedia article about RISC. |
| XAP_Processors_for_ASIC_and_FPGA Designs 16- and 32-bit processor cores to embed in application specific integrated circuits, ASICs; coded in Verilog language, provided as soft IP (Intellectual Property) cores. Cambridge Consultants |
| RISC_vs__CISC__The_Post-RISC_Era Detailed, balanced, historical analysis. [Ars Technica] (October, 1999) |
| Beyond_RISC__The_Post-RISC_Architecture Today's RISC processors are so far from RISC roots that they are no longer truly RISC. [Michigan State University, Department of Computer Science] (May, 1996) |
| Embedded_Computing__A_VLIW_Approach_to_Architecture,_Compilers_and_Tools By Joseph A. Fisher, Paolo Faraboschi, Cliff Young; Morgan Kaufmann, 2004, ISBN 1558607668. Technology is removing the gap between embedded and VLIW computing: high-performance methods that seemed too |
| Very_Long_Instruction_Word Growing entry, with links to many related topics. [Wikipedia] |
| VLIW_at_IBM_Research Very-Long Instruction Word architectures: an alternative way to organize processors. Instead of the trend toward hardware making complex decisions for scheduling machine-level instructions in programs |
| VLIW_Processors_and_Trace_Scheduling Descriptions, history, examples, references; in HTML, PDF, and in: The Computer Engineering Handbook, by Vojin Oklobdzija, CRC Press, 2001, ISBN 0849308852. |
| Code-morphing__Fresh_as_a_DAISY On translating software between x86-based and VLIW processors, mainly IBM's code-morphing chip similar to Transmeta's. (November 29, 2000) |
| Antique_Software__Turbo_Pascal_v5_5 Article by David Intersimone. Also Turbo Pascal v5.5 download. |
| Borland_Pascal_Version_History Photos and detailed information about all Borland Pascal versions, from 1.0 to 7.0. |
| comp_lang_pascal_borland_FAQ The Frequently Asked Questions for this Usenet newsgroup. |
| Frank\'s_Borland_Pascal_programs Programs and units for Borland Pascal. Mostly text-manipulation. |
| Graphic_Vision Graphical Application Framework for Borland Pascal. Brings the Windows look, including BWCC custom controls, to DOS applications. |
| V-Dragon Culturecom and IBM joint development, embeds Multilingual Character Generating Engine (MCGE) and Midori Linux on PowerPC 405 processor. Puts a Chinese character (pictogram) generator on chip, simplifi |
| IBM_Unleashes_4_7_GHz_POWER6_Microprocessor Two core, 64-bit, doubles speed of prior generation POWER5, uses nearly equal power to run and cool it; has 790 million transistors via IBM 65nm lithography, result of 5 year R&D effort. Descripti |
| LinuxSH_Wiki Information on port of Linux kernel to SuperH and SH-Mobile family of processors from Renesas Technology, and STMicroelectronics, the former SuperH, Inc., and legacy parts from Hitachi. |
| Renesas_Technology_Corp___SuperH_RISC_Engine_Family Product page on embedded RISC for high performance per unit of cost and power use (MIPS/W), miniaturization. Series: SH-2, SH-3, SH-4. News, FAQs, documents, data, diagrams. |
| STMicroelectronics_N_V___Microcontrollers Product page on embedded RISC processors. Series: ST6, ST7, ST10; 8- and 16-bit. Forums, FAQs, documents, data, diagrams. English, Chinese, Japanese, French, Italian. |
| SuperH Growing article, with links to many related topics. Wikipedia. |
| Community_licensing_of_Jini Information on licensing Jini technology. |
| Barrel_Processor Growing article, with links to many related topics. [Wikipedia |
| Bull_Gamma_60,_1958 Design analysis, with references, links, PostScript download, by Mark Smotherman, computer science professor, Clemson University. |
| Gamma_60 Introductory analysis, translated from French, by Jean Bellec. |
| IP3000_Family_Processors Product page with data on IP3023 wireless network processor. Ubicom, Inc. |
| Soft_Peripherals Article describes Ubicom IP3023 processor. It appears to have built-in Ethernet interface, USB controller, PCI and ISA bus interfaces, PCMCIA slot, synchronous DRAM controller, set of UARTs, etc., but |
| Volume_Multi-Processor_Systems__Part_2 Article on chip and thread level parallelism, fine grained multithreading, SMT and CMP. Ace's Hardware. (June 20, 2002) |
| DSPP__PA-RISC_Architecture System documentation for 32- and 64-bit PA-RISC processors. Hewlett-Packard Development Company, L.P. |
| The_OpenPA_Project Help and information for users of PA-RISC HP 9000 workstations and servers. Topics: hardware, computers, software, news. |
| PA-RISC_Family Growing article, with links to many related topics. [Wikipedia] |